Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors

We propose an analytical model to compute the potential distribution in gate underlap double-gate symmetric MOS transistors in the subthreshold condition G_gs < V_th . Gate underlap increases the effective channel length, which results in reducing the short-channel effect and, hence, relaxing the constraint on silicon body thickness. We use the proposed model to obtain suitable gate underlap length and silicon thickness for iso subthreshold slope and drain-induced-barrier lowering. Gate fringing field, modulating the potential in gate underlapped regions, is modeled using a conformal mapping technique. Extensive simulations were carried out to confirm the validity of our model to gate lengths ~20 nm.