Abstract :
In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG tunnel FET), for which the simulations show significant improvements compared with single-gate devices using a gate dielectric. For the first time, DG tunnel FET devices, which are using a high-gate dielectric, are explored using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2D nature of tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, tunnel FETs with a high-kappa gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 times 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance.
Keywords :
dielectric materials; field effect transistors; tunnelling; band-to-band tunneling; double-gate tunnel FET; double-gate tunnel field-effect transistor; gate-dielectric surface; high-k gate dielectric; single-gate devices; threshold voltage shift; voltage 1.8 V; Dielectric devices; Double-gate FETs; Gate leakage; MOSFET circuits; P-i-n diodes; Silicon germanium; Switches; Temperature; Threshold voltage; Tunneling; Band-to-band tunneling; double gate (DG); gated p-i-n diode; high-$kappa$ dielectric; subthreshold swing; tunnel field-effect transistor (FET);