Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications

We report a novel electro-thermally coupled power-optimization methodology for future transistors. The methodology self-consistently yields the globally optimized total power and the corresponding temperature as a function of delay for a given set of transistors (bulk, double-gate FET, fully depleted SOI, and partially depleted SOI) at future technology nodes. When SPICE models are not necessarily available and simple device models are highly inadequate because of complex 2D device effects, these derived power/temperature versus delay curves serve as a comprehensive standard to compare any two transistors for future technology-node device selections. Because the power optimization is global (over various transistor parameters and includes leakage as well as dynamic power) and is self-consistently coupled to electro-thermal models, the methodology provides the optimum operational supply voltage (V_dd) and the device parameters (body thickness, equivalent oxide thickness, and gate metal work function) for future transistors targeting 45-nm technology node. Furthermore, it can be used to provide insight into advance nodes, device-specific hot-spot problems, multiple V_t, V_dd design for different functional blocks, transistor design, and evaluating the efficacy of novel thermal solutions such as superior thermal conductivity and subambient cooling.