DocumentCode
1016535
Title
Improved CV/I Methodology to Accurately Predict CMOS Technology Performance
Author
Yeh, Ping-Chin ; Nayak, Deepak K. ; Gitlin, Daniel
Author_Institution
Xilinx Inc., San Jose
Volume
54
Issue
7
fYear
2007
fDate
7/1/2007 12:00:00 AM
Firstpage
1760
Lastpage
1762
Abstract
Conventional CV/I methodology is shown to be inadequate in projecting circuit performance of advanced technologies. The calculation can result in over 100% error on performance estimates compared to the silicon data. In this brief, we present an improved CV/I model that predicts performance within 3% error against ring oscillator delays over different technology nodes. The model is highly scalable and can be used as figure of merit for future technology performance assessment.
Keywords
CMOS integrated circuits; integrated circuit modelling; CMOS technology performance; CV/I methodology; CV/I model; figure of merit; ring oscillator delays; silicon data; CMOS technology; Circuit optimization; Delay; Inverters; Parasitic capacitance; Performance gain; Ring oscillators; Semiconductor device modeling; Silicon; Transistors; CMOS; delay; figure of merit (FOM); model; technology assessment; transistor;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2007.898043
Filename
4252391
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