DocumentCode
1016789
Title
Use of the polysilicon gate layer for local interconnect in a CMOS technology incorporating LDD structures
Author
El-Diwany, M.H. ; Brassington, M.P. ; Tuntasood, P. ; Razouk, R.R. ; Poulter, M.W.
Author_Institution
Fairchild Res. Center, Palo Alto, CA, USA
Volume
35
Issue
9
fYear
1988
fDate
9/1/1988 12:00:00 AM
Firstpage
1556
Lastpage
1558
Abstract
In conventional single-level polysilicon technologies, the polysilicon gate layer can be used as an interconnect layer through buried contacts between polysilicon and one type of junction (usually n +) in the underlying substrate. The formation and characteristics of buried contacts between n+ and p+ junctions and a single polysilicon gate layer are discussed. In addition, it is shown that the obstacles posed by the inclusion of oxide-sidewall spacers (common in present-day VLSI CMOS technologies) are surmountable with respect to the formation of useful buried contacts and the resultant local interconnect level that they provide
Keywords
CMOS integrated circuits; VLSI; elemental semiconductors; integrated circuit technology; silicon; CMOS technology; IC technology; LDD structures; VLSI; buried contacts; lightly doped drain; local interconnect; oxide-sidewall spacers; polycrystalline Si gate layer; semiconductor; CMOS technology; Conductors; Contact resistance; Dielectric substrates; Etching; Laboratories; MOSFETs; Silicon; Space technology; Very large scale integration;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.2591
Filename
2591
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