DocumentCode :
1019209
Title :
Design optimization of low-power high-performance DSP building blocks
Author :
Gemmeke, Tobias ; Gansen, Michael ; Stockmanns, Heinrich J. ; Noll, Tobias G.
Author_Institution :
Chair of Electr. Eng. & Comput. Syst., RWTH Aachen Univ., Germany
Volume :
39
Issue :
7
fYear :
2004
fDate :
7/1/2004 12:00:00 AM
Firstpage :
1131
Lastpage :
1139
Abstract :
In recent years, power dissipation along with silicon area has become the key figure in chip design. The increasing demands on system performance require high-performance digital signal processing (DSP) systems to include dedicated number-crunching units as individually optimized building blocks. The various design methodologies in use stress one of the following figures: power dissipation, throughput, or silicon area. This paper presents a design methodology reducing any combination of cost drivers subject to a specified throughput. As a basic principle, the underlying optimization regards the existing interactions within the design space of a building block. Crucial in such optimization is the proper dimensioning of device sizes in contrast to the common use of minimal dimensions in low-power implementations. Taking the design space of an FIR filter as an example, the different steps of the design process are highlighted resulting in a low-power high-throughput filter implementation. It is part of an industrial read-write channel chip for hard disks with a worst case throughput of 1.6 GSamples/s at 23 mW in a 0.13-μm CMOS technology. This filter requires less silicon area than other state-of-the-art filter implementations, and it disrupts the average trend of power dissipation by a factor of 6.
Keywords :
FIR filters; design engineering; digital signal processing chips; low-power electronics; optimisation; 0.13 micron; 23 mW; CMOS technology; FIR filter; chip design; design optimization; design process; device sizes; digital signal processing systems; filter implementations; hard disks; low-power high-performance DSP building blocks; number-crunching units; power dissipation; read-write channel chip; silicon area; system performance; CMOS technology; Chip scale packaging; Design methodology; Design optimization; Digital signal processing; Digital signal processing chips; Finite impulse response filter; Power dissipation; Silicon; Throughput; CMOS; DSP building block; FIR filter; VLSI; device sizing; high-speed; low-power; optimization; physically oriented design;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2004.829395
Filename :
1308587
Link To Document :
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