Title :
A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM
Author :
Nakamura, Kazuyuki ; Oguri, Takashi ; Atsumo, Takao ; Takada, Masahide ; Ikemoto, Atsushi ; Suzuki, Hisamitsu ; Nishigori, Tadashi ; Yamazaki, Tohru
Author_Institution :
NECP Corp., Kanagawa, Japan
fDate :
11/1/1992 12:00:00 AM
Abstract :
The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure
Keywords :
BiCMOS integrated circuits; SRAM chips; emitter-coupled logic; transistor-transistor logic; 0.55 micron; 3.3 V; 4 Mbit; 6 ns; 8 ns; BiCMOS; CMOS level; ECL signal level; SRAM; TTL I/O interface; bipolar sensing circuits; decoder gate stages; design method; high-speed address access times; level converter; low threshold voltage nMOSFETs; metal mask programmed; triple-well structure; BiCMOS integrated circuits; CMOS memory circuits; CMOS process; CMOS technology; Decoding; Design methodology; MOSFETs; Random access memory; Signal processing; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
