A 5-V-only 16-Mb flash memory with sector erase mode

Author

Jinbo, Toshikatsu ; Nakata, Hidetoshi ; Hashimoto, Kiyokazu ; Watanabe, Takeshi ; Ninomiya, Kazuhisa ; Urai, Takahiko ; Koike, Mikio ; Sato, Tatsuo ; Kodama, Noriaki ; Oyama, Ken-ichi ; Okazawa, Takeshi

Author_Institution

NEC Corp., Kanagawa, Japan

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1547

Lastpage

1554

Abstract

A 5-V-only 16-Mb CMOS flash memory with sector erase mode is described. An optimized memory cell with diffusion self-aligned drain structure and channel erase are keys to achieving 5-V-only operation. By adopting this erase method and row decoders to apply negative bias, 512-word sector erase can be realized. The auto chip erase time of 4 s has been achieved by adopting 64-b simultaneous operation and improved erase sequence. The cell size is 1.7 μm×2.0 μm and the chip size is 6.3 mm×18.5 mm using 0.6-μm double-layer metal triple-well CMOS technology

Keywords

CMOS integrated circuits; integrated memory circuits; 0.6 micron; 16 Mbit; 4 s; 5 V; channel erase; diffusion self-aligned drain structure; double-layer metal; flash memory; negative bias; optimized memory cell; row decoders; sector erase mode; triple-well CMOS technology; CMOS process; CMOS technology; Circuits; Decoding; Flash memory; Lithography; MOS devices; National electric code; Tungsten; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165335

Filename

165335