DocumentCode
1020091
Title
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
Author
Young, Ian A. ; Greason, Jeffrey K. ; Wong, Keng L.
Author_Institution
Intel Corp., Hillsboro, OR, USA
Volume
27
Issue
11
fYear
1992
Firstpage
1599
Lastpage
1607
Abstract
A microprocessor clock generator based on an analog phase-locked loop (PLL) is described for deskewing the internal logic control lock to an external system lock. This PLL is fully generated onto a 1.2-million-transistor microprocessor in 0.8- mu m CMOS technology without the need for external components. It operates with a lock range from 5 to 110 MHz. The clock skew is less than 0.1 ns, with a peak-to-peak jitter of less than 0.3 ns for a 50-MHz system clock frequency.<>
Keywords
CMOS integrated circuits; clocks; mixed analogue-digital integrated circuits; phase-locked loops; timing circuits; 0.8 micron; 5 to 110 MHz; CMOS technology; PLL clock generator; clock skew; deskewing; internal logic control lock; lock range; microprocessor clock; phase-locked loop; CMOS technology; Clocks; Delay; Driver circuits; Filters; Jitter; Microprocessors; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.165341
Filename
165341
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