Equivalence checking for digital circuits

Integrated circuit technology has made it possible to produce chips with several millions of transistors. However, the increasingly more complex digital circuit designs and limited time constraints only add to the pressure during the implementation process. Traditional functional verification based on simulation has, during the design creation phase, reached its limits. Thus alternatives to simulation are being used. The most important alternative is equivalence checking, known also as formal verification. With equivalence checking, the highly automated analysis of the different levels of digital circuit design is performed. A comprehensive formal verification solution at every stage in the design-flow is the main approach for today´s digital circuit design. Equivalence checking uses mathematical proof algorithms, then verifies every node in the design. Thus, equivalence checking guarantees 100% verification coverage without the need for test vectors. This is the big advantage over the traditional practice of functional verification by simulation that is directed by a set of test vectors.