Title :
An architecture for high-performance/small-area multipliers for use in digital filtering applications
Author :
Kwentus, Alan Y. ; Hung, Hing-Tsun ; Willson, Alan N., Jr.
Author_Institution :
Dept. of Electr. Eng., California State Univ., Los Angeles, CA, USA
fDate :
2/1/1994 12:00:00 AM
Abstract :
A multiplier architecture and encoding scheme well suited for programmable digital filtering applications is described. The multiplier´s partial product recoding scheme uses only simple multiplexers and takes advantage of a RAM that stores filter coefficients. We use an optimized 20-transistor full-adder cell in the carry-save adder array, and a carry-select vector-merge adder produces the final output. An integrated circuit comprising an ll-b by ll-b multiplier using second-order recoding has been fabricated in 2-μm CMOS technology. It operates in 22 ns and its core occupies 1.53 mm2. Also, an ll-b by 16-b multiplier using third-order recoding has been fabricated through MOSIS in 1.2-μm CMOS technology. Its core occupies 0.9 mm2 and it operates in 19 ns
Keywords :
CMOS integrated circuits; adders; carry logic; digital filters; integrated logic circuits; logic arrays; multiplying circuits; 1.2 mum; 19 ns; 2 mum; 20-transistor full-adder cell; 22 ns; CMOS technology; MOSIS; carry-save adder array; carry-select vector-merge adder; encoding scheme; multiplier architecture; partial product recoding scheme; programmable digital filtering; small-area multipliers; third-order recoding; Adders; CMOS integrated circuits; CMOS technology; Digital filters; Encoding; Filtering; Hardware; Integrated circuit technology; Multiplexing; Signal processing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
