Reconfiguring fault-tolerant two-dimensional array architectures

Author

Davis, Nathaniel J., IV ; Gray, F. Gail ; Wegner, Joseph A. ; Lawson, Shannon E. ; Murthy, Vinay ; White, Tennis S.

Author_Institution

Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA

Volume

14

Issue

2

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

60

Lastpage

69

Abstract

Circuit complexities reduce overall reliability and mean-time-between-failure rates of today´s very large processing arrays. Our integrated, three-level hierarchy of reconfiguration methods provides reasonable levels of fault tolerance for such systems. Operating in a completely distributed fashion, the hierarchy does not require that any components be fault free. It significantly improves array reliability by using a combination of transient fault rollback techniques and local and global reconfiguration algorithms.<>

Keywords

fault tolerant computing; parallel architectures; reconfigurable architectures; circuit complexities; fault-tolerant two-dimensional array architectures reconfiguration; global reconfiguration algorithms; local reconfiguration algorithm; mean-time-between-failure; reliability; three-level hierarchy; transient fault rollback techniques; very large processing arrays; Circuit faults; Complexity theory; Fault tolerance; Fault tolerant systems; Hardware; Integrated circuit reliability; Large-scale systems; Resource management; Runtime; Very large scale integration;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.272839

Filename

272839