A VLSI architecture for real-time and flexible image template matching

A modular and flexible architecture that realizes a parallel algorithm for real-time image template matching is described. Symmetrically permuted template data (SPTD) are employed in this algorithm to obtain a processing structure with a high degree of parallelism and pipelining, reduce the number of memory accesses to a minimum, and eliminate the use of delay elements that render the dimension of search area to be processed unchangeable. The inherent temporal parallelism and spatial parallelism of the algorithm are fully exploited in developing the hardware architecture. The latter, which is mainly constructed from two types of basic cells, exhibits a high degree of modularity and regularity. The architecture is especially suitable for applications in which adjustments of the dimension of the search area are constantly required. A hardware prototype has been constructed using standard integrated circuits for moving-object detection and interframe motion estimation. It is capable of operating on a search area of size up to 256×256 pixels in real time