Composite second-generation current conveyor with reduced parasitic resistance

A composite second-generation current conveyor (CCII) with positive or negative current transfer, implemented from two identical CCII⁺s having the same value for their bias currents, is described. The parasitic output resistance which appears on port X is considerably reduced from this implementation, without increase of the power consumption. SPICE simulation results using the CCII⁺ in its translinear form and implemented from bipolar transistors are given. They confirm the theoretical approach and underline the possibility of the implementation. This is revealed to be more efficient than existing approaches, principally either with low values for the bias current or a low value for the load connected at X