• DocumentCode
    104172
  • Title

    Comprehensive Study of the Complex Dynamics of Forward Bias-Induced Threshold Voltage Drifts in GaN Based MIS-HEMTs by Stress/Recovery Experiments

  • Author

    Lagger, P. ; Reiner, M. ; Pogany, Dionyz ; Ostermaier, C.

  • Author_Institution
    Vienna Univ. of Technol., Vienna, Austria
  • Volume
    61
  • Issue
    4
  • fYear
    2014
  • fDate
    Apr-14
  • Firstpage
    1022
  • Lastpage
    1030
  • Abstract
    The transient recovery characteristics of the threshold voltage drift (ΔVth) of GaN-based HEMTs with a SiO2 gate dielectric induced by forward gate bias stress are systematically and comprehensively investigated for stress times from 100 ns to 10 ks, recovery times from 4 μs to 10 ks, and stress biases from 1 to 7 V. The measured recovery data are analyzed using the concept of capture emission time maps. It is shown that the observed data cannot be explained by simple first-order defect kinetics. It is revealed that the recovery curves for constant stress times scale with the stress bias. Furthermore, the shape of the recovery curves changes from concave to convex with increasing stress time, independent of the stress bias. For short stress times and low stress bias, a dominant rate limiting effect of the III/N barrier layer is proposed. Defect-related physical processes with a broad distribution of characteristic time constants are discussed to explain the logarithmic time dependency of ΔVth stress and recovery, at which the role of the Coulomb feedback effect, complex defects, and spatially distributed defects are considered.
  • Keywords
    III-V semiconductors; MIS structures; gallium compounds; high electron mobility transistors; silicon compounds; stress relaxation; wide band gap semiconductors; GaN; MIS-HEMT; SiO2; capture emission time; complex dynamics; defect related physical processes; dominant rate limiting effect; forward bias induced threshold voltage drifts; gate dielectric; semiconductor device stress; stress bias; transient recovery; voltage 1 V to 7 V; Dielectrics; Gallium nitride; HEMTs; Logic gates; MODFETs; Stress; Threshold voltage; AlGaN/GaN; MOS; defect models; forward gate bias stress; high electron mobility transistor (HEMT); interface states; metal insulator semiconductor (MIS); multistate defects; power switching applications; reliability; threshold voltage drift; trapping;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2014.2303853
  • Filename
    6740848