Physical design alternatives for RISC workstation packaging

A comparative study of packaging architectures for state-of-the-art multichip workstation-level reduced instruction set computers (RISCs) is presented. Single-chip on high-density printed wiring board packaging and several multichip module (MCM) strategies on ceramic and silicon substrate are included. These approaches are assessed, given current state-of-the-art manufacturing capabilities and projections for the foreseeable future. The study was conducted with AUDiT Version 4.2, a simulation tool for evaluating the physical design of electronic systems. The model RISC workstation was derived from a commercial computer. Good performance correlations between predicted data and this commercial workstation were obtained. The best performance in each case is obtained close to the tiling limit of the packages, or chips, for single chip, or multichip, modules, respectively. Results also show that the performance boundaries between alternative packaging architectures become blurred. Guidelines for improving each packaging architecture are given