Routability-driven technology mapping for lookup table-based FPGA´s

A new algorithm for technology mapping of lookup table-based Field-Programmable Gate Arrays (FPGA´s) is presented. It has the capability of producing compact designs (minimizing the number of cells (CLB´s)), as well as the flexibility of trading routability with compactness of a design. Research in this area has focussed on minimizing the number of cells. However, minimizing the number of cells without regard to routability is ineffective. Since placement and routing is really the most time-consuming part of the FPGA design process, producing a routable design with a slightly larger number of cells is preferable than producing a design using fewer cells which is difficult to route, or in the worst case unroutable. We have implemented our algorithm in the Rmap program, and studied routability of two other mappers with respect to Rmap. Rmap produces mappings with better routability characteristics, and more significantly Rmap produces routable mappings when other mappers do not