Extended SET Pulses in Sequential Circuits Leading to Increased SE Vulnerability

Mixed mode simulations and heavy-ion experiments indicate the presence of multinode charge collection in advanced technologies. For logic circuits, such charge collection may result in concatenation of transients, extending the width of SETs. Mixed-mode simulations of a 4-bit adder circuit indicate that the increase in SET pulse width due to two-node charge collection can be as high as 75%. An analytical model for the increase in the SET width is developed showing the increase in SET width is proportional to the width of the individual transients, the relative delay between charge collection nodes, and the circuit topology.