Title :
Gain-compensated sample-and-hold circuit for high frequency application
Author :
Di Cataldo, G. ; Palmisano, G. ; Palumbo, Gaetano
Author_Institution :
Catania Univ., Italy
fDate :
7/22/1993 12:00:00 AM
Abstract :
A novel and fast and accurate sample-and-hold circuit is presented which can be designed using conventional single stage amplifiers. The offset contribution to the output voltage is intrinsically compensated and the clock-feedthrough error can be reduced by slightly changing the clock phase scheme.
Keywords :
compensation; sample and hold circuits; HF applications; S/H topology; clock phase scheme; clock-feedthrough error; gain compensation; high frequency application; high speed; offset contribution; offset voltage; output voltage; sample/hold circuit; single stage amplifiers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19930903
