Title :
Multiple Bit Upsets and Error Mitigation in Ultra-Deep Submicron SRAMS
Author :
Mavis, D.G. ; Eaton, P.H. ; Sibley, M.D. ; Lacoe, R.C. ; Smith, E.J. ; Avery, K.A.
Author_Institution :
Microelectron. Res. Dev. Corp., Albuquerque, NM
Abstract :
Recent measurements of the SEU (single-event upset) cross-section for 6 T SRAMs fabricated in a nano-scale commercial CMOS process were performed. Results indicated that the dominant upset mechanism was associated with multiple-cell upsets (MCUs) strikes on PMOS transistors. The dominance of the MCU cross section favors the use of a block architecture with widely spaced word bits and the use of EDAC (error detect and correct) along with periodic memory scrubbing to prevent the integration of single-bit errors.
Keywords :
CMOS digital integrated circuits; SRAM chips; CMOS process; PMOS transistors; error detect and correct; error mitigation; multiple bit upsets; multiple-cell upsets; periodic memory scrubbing; single-bit errors; single-event upset; ultra-deep submicron SRAM; CMOS process; CMOS technology; Circuit testing; Error correction; Event detection; MOSFETs; Performance evaluation; Random access memory; SRAM chips; Single event upset; Error detect and correct; heavy-ion testing; multiple bit upset; multiple cell upset; single event effects; single event transient; single event upset; static random access memory;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2008.2006893
