Laser Verification of On-Chip Charge-Collection Measurement Circuit

Author

Amusan, Oluwole A. ; Fleming, Patrick R. ; Bhuva, Bharat L. ; Massengill, Lloyd W. ; Witulski, Arthur F. ; Balasubramanian, Anupama ; Casey, Megan C. ; McMorrow, Dale ; Nation, Sarah A. ; Barsun, Frederick ; Melinger, Joseph S. ; Gadlage, Matthew J. ; Lov

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN

Volume

55

Issue

6

fYear

2008

Firstpage

3309

Lastpage

3313

Abstract

An on-chip charge-collection measurement circuit has been designed and fabricated in a 130 nm bulk CMOS process. Laser testing is used to verify the effectiveness of the on-chip charge-collection circuit technique for characterizing single event charge collection in advanced technologies. The on-chip charge-collection measurement circuit is used as an investigative tool for examining the effects of parasitic bipolar amplification for deep-submicron PMOS devices.

Keywords

CMOS integrated circuits; integrated circuit design; laser beam applications; materials testing; CMOS; deep-submicron PMOS devices; laser testing; laser verification; on-chip charge-collection measurement circuit; parasitic bipolar amplification; size 130 nm; CMOS logic circuits; CMOS technology; Charge measurement; Circuit testing; Cranes; Current measurement; Diodes; MOS devices; Single event upset; Transistors; ${rm n}^{+}$ diode; ${rm p}^{+}$ diode; Charge collection; NMOS; PMOS; n-well potential collapse; parasitic bipolar transistor; single event characterization;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2008.2007123

Filename

4723786