Design techniques and test methodology for low-power TCAMs

Author

Mohan, Nitin ; Fung, Wilson ; Wright, Derek ; Sachdev, Manoj

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont.

Volume

14

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

573

Lastpage

586

Abstract

Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also propose a novel test methodology for various TCAM components. The proposed test algorithms show significant improvement over the existing algorithms both in test complexity and fault coverage

Keywords

content-addressable storage; integrated circuit testing; logic testing; low-power electronics; associative memories; design techniques; fault coverage; low-power TCAMs; priority encoder; ternary content addressable memories; test complexity; test methodology; Associative memory; CADCAM; Circuit testing; Computer aided manufacturing; Costs; Energy consumption; Logic testing; Quality of service; Radar tracking; Random access memory; Associative memories; content addressable memory (CAM); low power; priority encoder (PE); testing;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2006.878206

Filename

1661598