VERITAS: A 128-Channel ASIC for the Readout of pnCCDs and DEPFET Arrays for X-Ray Imaging, Spectroscopy and XFEL Applications

VERITAS (VErsatile Readout based on Integrated Trapezoidal Analog Shapers) is the first 128-channel ASIC developed to read out both the pnCCDs and the DEPFET arrays produced at the MPI-Halbleiterlabor in Munich. These detectors are used in a large variety of scientific applications, ranging from high-speed optical astronomy and X-ray astronomy to the new X-ray Free Electron Laser sources. The main concept of VERITAS is to provide a flexible readout chip able to cope not only with different kinds of detectors, but also with a large set of operating conditions that may require very different noise thresholds and input dynamic ranges. These can vary by more than two orders of magnitude. Every analog channel of VERITAS provides a trapezoidal weighting function. This filtering strategy had never been applied to the pnCCD before. The very first measurements obtained coupling VERITAS with a 128 × 256 pnCCD are shown. With a readout time of 4 μs/line a noise of 3.9 electrons has been measured in the highest gain mode. The resolution obtained on the Mn-Kα peak of a ⁵⁵Fe source is 136 eV for single events. A noise of 30 electrons has been achieved in the lowest gain mode at a speed of 6.4 μs/line. In this low gain setting an input charge up to 2 5 × 10⁵ electrons can be processed. These striking results fulfill the requirements of the main foreseen applications of large-size pnCCDs. In order to further improve the performance and the flexibility of the ASIC, a second version based on a fully differential architecture has been designed. The new topology allows one also to switch with the same ASIC between the source follower and drain current readout of the DEPFET sensors and to reach a processing time of about 2-3 μs/line with an electronics noise ≤10 el. For this reason the second version of VERITAS is very attractive for the proposed ESA X-ray astronomy mission ATHENA.