Title :
A mux-based High-Performance Single-Cycle CMOS Comparator
Author :
Lam, Hing-Mo ; Tsui, Chi-ying
Author_Institution :
Hong Kong Univ. of Sci. & Technol., Hong Kong
fDate :
7/1/2007 12:00:00 AM
Abstract :
In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure. By doing so, the fast dynamic MUX significantly improves the overall delay of the high-fan-in comparators. At the same time, a novel high-performance static priority encoder is proposed to generate the control signal for the MUX. A 64-bit MUX-based comparator has been built and compared with the existing fastest single-cycle design in the study by Lam and Tsui (2006). From both the post-layout simulation and test-chip measurement results, it is shown that the performance is improved by around 28%.
Keywords :
CMOS logic circuits; comparators (circuits); digital arithmetic; MUX; digital arithmetic; high-fan-in CMOS comparator; high-speed integrated circuits; parallel-MSB-checking; post-layout simulation; single-cycle CMOS comparator; static priority encoder; test-chip measurement; two-stage comparator; word length 64 bit; Adders; Circuits; Clocks; Delay; Digital signal processing; Logic; Pipeline processing; Process design; Signal generators; Signal processing algorithms; Comparator; digital arithmetic; high-speed integrated circuits; parallel-MSB-checking;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2007.899856
