Title :
The n+-IPOS scheme and its applications to IC´s
Author :
Arita, Y. ; Kato, K. ; Sudo, T.
Author_Institution :
Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, Japan
fDate :
6/1/1977 12:00:00 AM
Abstract :
The n+-IPOS scheme, a new isolation technique, has been developed and applied to fabricate integrated circuits. A propagation delay of 105 ps/gate has been obtained for an NTL circuit fabricated using this scheme.
Keywords :
Charge carrier processes; Circuits; Electron emission; Epitaxial layers; Impurities; Lighting; Oxidation; Propagation delay; Silicon; Temperature;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/T-ED.1977.18816
