• DocumentCode
    1056834
  • Title

    The n+-IPOS scheme and its applications to IC´s

  • Author

    Arita, Y. ; Kato, K. ; Sudo, T.

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Musashino-shi, Tokyo, Japan
  • Volume
    24
  • Issue
    6
  • fYear
    1977
  • fDate
    6/1/1977 12:00:00 AM
  • Firstpage
    756
  • Lastpage
    757
  • Abstract
    The n+-IPOS scheme, a new isolation technique, has been developed and applied to fabricate integrated circuits. A propagation delay of 105 ps/gate has been obtained for an NTL circuit fabricated using this scheme.
  • Keywords
    Charge carrier processes; Circuits; Electron emission; Epitaxial layers; Impurities; Lighting; Oxidation; Propagation delay; Silicon; Temperature;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1977.18816
  • Filename
    1479008
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1056834