Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture

The increasing gap between design productivity and chip complexity and the emerging systems-on-chip (SoCs) architectural template have led to the wide utilization of reusable hard intellectual property (IP) cores. Macro block-based physical design implementation needs to find a well-balanced solution among chip area, on-chip communication energy, and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire tradeoff curve among the network energy, chip area, and critical communication path delay at the floorplanning stage based on two real-life application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This tradeoff profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems.