DocumentCode :
1062438
Title :
Enhanced capacity CCD
Author :
Chatterjee, Pallab K. ; Tasch, Alf, Jr. ; Fu, Horng-Sen ; Holloway, Thomas C.
Author_Institution :
Texas Instruments Inc., Dallas, TX
Volume :
25
Issue :
12
fYear :
1978
fDate :
12/1/1978 12:00:00 AM
Firstpage :
1374
Lastpage :
1382
Abstract :
This paper introduces a method for enhancing the charge capacity and lowering the leakage current in CCD´s. The two-phase coplanar electrode structure is chosen as a vehicle for demonstrating the concept. The charge capacity enhancement is achieved by a combination of p-type and n-type implantations. This method of charge capacity enhancement relies on the increase of depletion capacitance in the storage well region of the CCD, as contrasted with other methods which increase the surface potential swing. A charge capacity analysis is undertaken and design constraints to provide maximum charge capacity are described. Results of measurements on the first test structure show 25-50-percent increase in charge capacity for buried-channel CCD´s and 66-166-percent increase in charge capacity for surface-channel CCD´s. A 2X-8X reduction in leakage current has been observed in these CCD´s. The increased capacity and decreased leakage current should result in improved performance of CCD´s in memory, signal processing, and imaging applications.
Keywords :
Capacitance; Charge coupled devices; Clocks; Current measurement; Design optimization; Electrodes; Implants; Leakage current; Vehicles; Voltage;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1978.19358
Filename :
1479752
Link To Document :
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