Title :
Simultaneous Switching Noise: The Relation between Bus Layout and Coding
Author :
Rossi, Daniele ; Nieuwland, André K. ; Metra, Cecilia
Author_Institution :
Univ. of Bologna, Bologna
Abstract :
As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated by a single switching wire and analyze the impact of transition-reducing encoding on SSN. They show that switching-pattern and layout considerations have a significant impact on TRE performance.
Keywords :
encoding; integrated circuit layout; integrated circuit reliability; switching circuits; system buses; IC reliability; bus coding; bus layout; device geometry shrink; integrated circuit; power supply voltage; simultaneous switching noise; transition-reducing encoding; worst-case condition; Clocks; Integrated circuit noise; Logic circuits; Logic design; Logic testing; Noise reduction; RLC circuits; Semiconductor device noise; Switching circuits; Voltage; IC; bus layout; coding techniques; power supply network; simultaneous switching noise; switching patterns; system reliability;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2008.25
