DocumentCode
1066005
Title
A programmable VLSI architecture for computing multiplication and polynomial evaluation modulo a positive integer
Author
Lu, Erl-Huei ; Harn, Lein ; Lee, Jau-Yien ; Hwang, Wen-Yih
Author_Institution
Dept. of Electr. Eng., Nat. Cheng King Univ., Tainan, Taiwan
Volume
23
Issue
1
fYear
1988
Firstpage
204
Lastpage
207
Abstract
A programmable VLSI architecture with regular, modular, expansible features is designed for computing AB mod N, AB+C mode N, and polynomial evaluation modulo N. The size of the resultant circuit can be easily expanded to improve the security of cryptosystems without making any change to its control circuit. The computing procedures for all N throughout the range of 0>
Keywords
VLSI; cryptography; digital arithmetic; computing procedures; cryptosystems; multiplication; polynomial evaluation modulo; programmable VLSI architecture; security; Added delay; Adders; Circuits; Computer architecture; Iterative algorithms; Polynomials; Public key cryptography; Security; Size control; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.280
Filename
280
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