The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation

The speedups derived from the exploitation of the waveform properties are discussed and simple procedures are provided to compute empirical upper bounds on the speed improvement when these properties are exploited. These upper bounds are used to explain the reasons for the variations in the speedups and to evaluate the performance of two circuit simulation algorithms based on nonlinear relaxation that are implemented in the SPLICE3 program. The first algorithm is an advanced version of the iterated timing analysis (ITA) algorithm that exploits the latency property. The second algorithm is a new event-driven multirate integration scheme, based on ITA, that exploits multirate behavior of circuits. It also uses a novel event-driven approach to handle step rejections called selective-backup