• DocumentCode
    1067553
  • Title

    Charge retention of floating-gate transistors under applied bias conditions

  • Author

    Wang, Samuel T.

  • Author_Institution
    Intel Corporation, Santa Clara, CA
  • Volume
    27
  • Issue
    1
  • fYear
    1980
  • fDate
    1/1/1980 12:00:00 AM
  • Firstpage
    297
  • Lastpage
    299
  • Abstract
    The nonvolatile memory-retention characteristics of floating-gate transistors with thin gate oxides are shown to be a strong function of both applied voltages and oxide thickness. Under the assumption that the charge loss mechanism is Fowler-Nordheim tunneling through the thin oxide, an expression is derived which allows the design of floating-gate transistors with optimized retention time.
  • Keywords
    Acceleration; Capacitance; Design optimization; Electrons; Equations; Nonvolatile memory; Temperature; Testing; Threshold voltage; Tunneling;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1980.19856
  • Filename
    1480649