An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs

Author

Tsukikawa, Yasuhiko ; Kajimoto, Takeshi ; Okasaka, Yasuhiko ; Morooka, Yoshikazu ; Furutani, Kiyohiro ; Miyamoto, Hiroshi ; Ozaki, Hideyuki

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan

Volume

29

Issue

4

fYear

1994

fDate

4/1/1994 12:00:00 AM

Firstpage

534

Lastpage

538

Abstract

An efficient back-bias (V_bb) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V_bb level of -1.44 V at V_cc=1.5 V, compared to a conventional system in which V_bb only reaches -0.6 V. HPC can pump without the threshold voltage (V_th) loss that conventional systems suffer. HPC is indispensable for 1.5-V DRAMs, because a V_bb level lower than -1.0 V is necessary to meet the limitations of the V_th, of the access transistor. HPC uses one NMOS and one PMOS pumping transistor. By adopting a triple-well structure at the pumping circuit area, the NMOS can be employed as a pumping transistor without minority carrier injection

Keywords

DRAM chips; MOS integrated circuits; VLSI; 1.5 V; DRAMs; MOS technology; access transistor; back-bias generator; hybrid pumping circuit; pumping circuit area; pumping transistors; triple-well structure; Capacitors; Character generation; Circuits; Hybrid power systems; MOS devices; Power dissipation; Random access memory; Region 2; Signal generators; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.280705

Filename

280705