• DocumentCode
    1069802
  • Title

    A 1-µm Mo—poly 64-kbit MOS RAM

  • Author

    Yanagawa, Fumihiko ; Kiuchi, Kazuhide ; Hosoya, Tetsuo ; Tsuchiya, Toshiaki ; Amazawa, Takao ; Mano, Tsuneo

  • Author_Institution
    Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan
  • Volume
    27
  • Issue
    8
  • fYear
    1980
  • fDate
    8/1/1980 12:00:00 AM
  • Firstpage
    1602
  • Lastpage
    1606
  • Abstract
    This paper describes a 1-µm 64-kbit MOS RAM using Mopoly technology. New 1-µm double-gate technology using molybdenum and polysilicon (Mo-poly technology) is proposed. In this technology, molybdenum and polysilicon are used for word lines and storage capacitor electrodes in the memory cell, respectively. Therefore, the propagation delay in a word line becomes extremely small and memory cell size is reduced. New two step annealing was developed for stabilizing an Mo-gate MOS structure. Design is optimized for 1-µm Si-gate FET´s in peripheral circuitry. A 1-µm Mo-poly 64-kbit MOS RAM was experimentally fabricated by using 1-µm process technologies. The cell size and die size were 8 µm × 8 µm and 3 mm µ 3 mm, respectively. Access time was less than 100 ns.
  • Keywords
    Aluminum; Circuits; Electrodes; FETs; Helium; MOS devices; Propagation delay; Random access memory; Read-write memory; Sheet materials;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/T-ED.1980.20077
  • Filename
    1480870