A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter

Author

Lu, Chi-Chang ; Lee, Tsung-Sum

Author_Institution

Nat. Formosa Univ., Yunlin

Volume

54

Issue

8

fYear

2007

Firstpage

658

Lastpage

662

Abstract

A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of the pipelined ADC. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. Employing double sampling and bias current scaling techniques, very competitive power consumption can be achieved. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.

Keywords

CMOS analogue integrated circuits; analogue-digital conversion; bootstrap circuits; sample and hold circuits; bias current scaling; bootstrapped switch; double-sampling technique; low-power CMOS; low-voltage power supply; pipelined analog-to-digital converter; power consumption; rail-to-rail signal swing; sample-and-hold circuit; timing-skew-insensitive Miller-capacitance-based circuit; word length 10 bit; Analog-digital conversion; Circuits; Clocks; Energy consumption; Pipelines; Power supplies; Sampling methods; Switches; Timing; Voltage; Analog-to-digital converter (ADC); CMOS analog integrated circuits; bootstrapped switch; low power; sample-and-hold (S/H) circuit;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2007.899449

Filename

4277931