DocumentCode
1075147
Title
A Leakage-Compensated PLL in 65-nm CMOS Technology
Author
Hung, Chao-Ching ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
56
Issue
7
fYear
2009
fDate
7/1/2009 12:00:00 AM
Firstpage
525
Lastpage
529
Abstract
A leakage compensation technique is presented to compensate the on-chip loop filter leakage for phase-locked loops in 65-nm complementary metal-oxide-semiconductor technology. Using the leakage compensation technique, the measured root-mean-square jitter is reduced to 3.10 ps when the output frequency is 950 MHz. This chip consumes 10 mW, and the active area is 0.14 mm2.
Keywords
CMOS integrated circuits; least mean squares methods; phase locked loops; CMOS technology; complementary metal-oxide-semiconductor technology; frequency 950 MHz; leakage compensation technique; leakage-compensated PLL; onchip loop filter leakage; phase-locked loops; root-mean-square jitter; Leakage compensation; nanoscale CMOS; phase-locked loop;
fLanguage
English
Journal_Title
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher
ieee
ISSN
1549-7747
Type
jour
DOI
10.1109/TCSII.2009.2020948
Filename
5075579
Link To Document