DocumentCode :
1077583
Title :
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test
Author :
Almukhaizim, Sobeeh ; Sinanoglu, Ozgur
Author_Institution :
Dept. of Comput. Eng., Kuwait Univ., Safat
Volume :
28
Issue :
2
fYear :
2009
Firstpage :
298
Lastpage :
302
Abstract :
Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, scan chains, and logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern and, thus, of delivering near-perfect peak power reductions. The proposed dynamic partitioning hardware allows for the partitioning reconfiguration on a per test pattern basis, hence delivering a solution that is test set independent, yet its quality is superior to that of any test set dependent solution.
Keywords :
integrated circuit testing; power consumption; dynamic partitioning; partitioning reconfiguration; peak shift power reduction; scan chain partitioning; test pattern; transition distribution; Dynamic partitioning; scan chain partitioning; test power reduction;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.2009159
Filename :
4757340
Link To Document :
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