Enhanced-performance 4K × 1 high-speed SRAM using optically defined submicrometer devices in selected circuits

An alternative method to coordinated scaling of overall device dimensions and structural parameters for increasing the bandwidth of static RAM´s is described in this paper. This method recognizes that the signal flow through a SRAM is uniquely determined. Attention is focused on the delay in the I/O buffers and sense amplifier circuits, where 50 percent of the access time delay occurs. It is shown that the introduction of only 48 selectively scaled, submicrometer transistors in these circuits can improve the access time by 35 percent theoretically. Using an edge-defined technique which requires only standard optical lithography for insertion of the selectively scaled transistors, the address access time has been improved from 36 to 25 ns. This is a 31-percent access time improvement, with only a 17-percent increase in power.