Title :
Advanced VLSI validated input security device employing data and hardware validation features
Author :
Iliev, V. ; Dlay, S.S. ; McLauchlan, M.R. ; Koelmans, A.M. ; Kinniment, D.J.
Author_Institution :
Dept. of Electr. & Electron. Eng., Newcastle Upon Tyne Univ., UK
fDate :
11/1/1989 12:00:00 AM
Abstract :
A fast CMOS VLSI device is described to execute the Data Encryption Standard (DES) algorithm. The device is known as the validated input security device (VISD) since it enables transmitted and received data to be validated through the use of parity checking. The device is directly compatible with most microprocessor families and it is also directly compatible with most DMA controllers. Full or partial parallelism can be used between encryption and input/output communication.
Keywords :
CMOS integrated circuits; application specific integrated circuits; cryptography; encoding; 56 bit key; 8 Mbit/s; 8 Mbit/s throughput; DES algorithm; Data Encryption Standard; VISD; fast CMOS VLSI device; hardware validation; input/output communication; parity checking; partial parallelism; validated input security device;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
