Cache-Conscious Thread Scheduling for Massively Multithreaded Processors

Author

Rogers, T.G. ; O´Connor, M. ; Aamodt, T.M.

Volume

33

Issue

3

fYear

2013

fDate

May-June 2013

Firstpage

78

Lastpage

85

Abstract

Highly multithreaded architectures introduce another dimension to fine-grained hardware cache management. The order in which the system´s threads issue instructions can significantly impact the access stream seen by the caching system. This article studies a set of economically important server applications and presents the cache-conscious wavefront scheduling (CCWS) hardware mechanism, which uses feedback from the memory system to guide the issue-level thread scheduler and shape the access pattern seen by the first-level cache.

Keywords

cache storage; microprocessor chips; multi-threading; parallel architectures; processor scheduling; CCWS; access stream; cache-conscious thread scheduling; cache-conscious wavefront scheduling hardware mechanism; caching system; fine-grained hardware cache management; highly multithreaded architectures; issue-level thread scheduler; massively multithreaded processors; memory system feedback; Cache storage; Computer architecture; Hardware; Memory management; Multithreading; Parallel processing; Program processors; Scheduling; CCWS; GPU; SIMD processors; cache; cache-conscious wavefront scheduling; locality; memory systems; parallel processors; thread scheduling;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/MM.2013.24

Filename

6487475