Title :
Threshold Voltage Shift Due to Charge Trapping in Dielectric-Gated AlGaN/GaN High Electron Mobility Transistors Examined in Au-Free Technology
Author :
Johnson, D.W. ; Lee, Rinus T. P. ; Hill, R.J.W. ; Man Hoi Wong ; Bersuker, Gennadi ; Piner, E.L. ; Kirsch, P.D. ; Harris, H.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
Abstract :
We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.
Keywords :
CMOS integrated circuits; III-V semiconductors; MOSFET; aluminium compounds; atomic layer deposition; contamination; dielectric thin films; electron traps; elemental semiconductors; gallium compounds; high electron mobility transistors; silicon; AlGaN-GaN; Au-free technology; CMOS line; Si; atomic layer deposition; charge trap-ping characteristics; dielectric-gated HEMT; dielectric-gated high electron mobility transistors; enhancement mode stability; gate stack; size 200 mm; threshold voltage engineering; threshold voltage shift; time constant traps; trap states; Aluminum gallium nitride; Charge carrier processes; Gallium nitride; HEMTs; Hafnium compounds; Logic gates; MODFETs; Au-free; GaN on Si; gate dielectric; power semiconductor devices; semiconductor–insulator interfaces;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2013.2278677
