Title :
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
Author :
Xu, Jiang ; Wolf, Wayne ; Zhang, Wei
Author_Institution :
Hong Kong Univ. of Sci. & Technol., Hong Kong
Abstract :
DWP, a new interconnect structure for asynchronous networks on chip in multiprocessing SoCs, yields higher throughput, consumes less power, suffers less from crosstalk noise, and requires less area than traditional interconnect structures. Its advantages stem from techniques including wave pipelining, double-data-rate transmission, interleaved lines, misaligned repeaters, and clock gating.
Keywords :
asynchronous circuits; multiprocessor interconnection networks; network-on-chip; pipeline processing; asynchronous NoC; clock gating; double-data-rate transmission; interleaved line; misaligned repeater; multiprocessing SoC; network-on-chip; wave-pipelined interconnect structure; Clocks; Crosstalk; Delay; Network-on-a-chip; Pipeline processing; Repeaters; Size control; Throughput; Transistors; Transmitters; asynchronous; double data rate; interconnect; low power; multiprocessor; network on chip; system on chip; wave pipeline;
Journal_Title :
Micro, IEEE
