Metallized ultra-shallow-junction device technology for sub-0.1 μm gate MOSFET´s

Author

Hisamoto, Digh ; Nakamura, Kaori ; Saito, Masayoshi ; Kobayashi, Nobuyoshi ; Kimura, Shin´ichiro ; Nagai, Ryo ; Nishida, Takashi ; Takeda, Eiji

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

41

Issue

5

fYear

1994

fDate

5/1/1994 12:00:00 AM

Firstpage

745

Lastpage

750

Abstract

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET´s. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability

Keywords

chemical vapour deposition; insulated gate field effect transistors; semiconductor technology; semiconductor-insulator boundaries; silicon; 10 to 200 nm; CVD; MOSFETs; contact characteristics; metallized ultra-shallow-junction device technology; parasitic diffusion-layer resistance; scalability; ultra-thin SOI-CMOS structure; Contact resistance; Electrodes; Fabrication; Impurities; MOSFET circuits; Metallization; Parasitic capacitance; Silicides; Tungsten; Wafer bonding;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.285027

Filename

285027