Title :
A novel multi-input floating-gate MOS four-quadrant analog multiplier
Author :
Mehrvarz, Hamid Reza ; Kwok, Chee Yee
Author_Institution :
Sch. of Electr. Eng., New South Wales Univ., Sydney, NSW, Australia
fDate :
8/1/1996 12:00:00 AM
Abstract :
A novel four-quadrant analog multiplier using multi-input floating-gate MOS (MFMOS) transistors has been designed and fabricated using a 2-μm double-poly double-metal P-well CMOS process. It is essentially based on the quarter-square technique which relies on the square-law characteristic of the MOS transistor in the saturation region. The multiplier is realized with only four MFMOS transistors and a current source. The input range is 100% of the supply voltage and accepts either differential, single-ended, or floating input signals. Measured nonlinearity and total harmonic distortion are 0.2% and 0.5%, respectively, under full scale input conditions. Input noise is 170 μV (rms), giving a 95 dB input dynamic range. The power dissipation is 1.1 mW and bandwidth is 12 MHz. Second-order effects on the multiplier performance have also been analyzed
Keywords :
CMOS analogue integrated circuits; analogue multipliers; harmonic distortion; integrated circuit noise; 1.1 mW; 12 MHz; 2 micron; current source; double-poly double-metal P-well CMOS process; floating input signals; floating-gate MOS circuits; four-quadrant analog multiplier; full scale input conditions; input dynamic range; input noise; multi-input circuits; nonlinearity; power dissipation; quarter-square technique; saturation region; second-order effects; square-law characteristic; total harmonic distortion; CMOS process; Circuits; Distortion measurement; Dynamic range; MOSFETs; Predistortion; Tail; Total harmonic distortion; Transconductance; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of