Title :
Analysis and modeling of bang-bang clock and data recovery circuits
Author :
Lee, Jri ; Kundert, Kenneth S. ; Razavi, Behzad
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA
Abstract :
A large-signal piecewise-linear model is proposed for bang-bang phase detectors that predicts characteristics of clock and data recovery circuits such as jitter transfer, jitter tolerance, and jitter generation. The results are validated by 1-Gb/s and 10-Gb/s CMOS prototypes using an Alexander phase detector and an LC oscillator.
Keywords :
CMOS digital integrated circuits; jitter; phase detectors; piecewise linear techniques; voltage-controlled oscillators; 1 Gbit/s; 10 Gbit/s; Alexander phase detector; CDR circuits; CMOS prototypes; LC oscillator; bang-bang loops; bang-bang phase detectors; binary PD; clock-and-data recovery circuits; jitter generation; jitter tolerance; jitter transfer; large-signal piecewise-linear model; metastability; nonlinear phase detector; Character generation; Circuits; Clocks; Detectors; Jitter; Phase detection; Piecewise linear techniques; Predictive models; Prototypes; Semiconductor device modeling; Bang-bang loops; CDR circuits; binary PDs; jitter; metastability; nonlinear phase detector;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.831600
