Digital matched filtering with pipelined floating point fast Fourier transforms (FFT´s)

A special floating point arithmetic technique for fast Fourier transform (FFT) processors has been developed. The implementation of a high-speed pipeline FFT matched filter using the method employs significantly fewer components than a fixed-point processor with an equivalent performance level. The special floating point process avoids the nonlinear effects of fixed-point processors while achieving performance levels of traditional floating point arithmetic. Computer simulations were used to examine the performance of the system for linear FM pulse compression under a variety of conditions. In a specific case, with 8 bits plus sign quantization of the complex I- and Q-mantissa words in the processor and a 12-stage (4096-coefficient) FFT convolver, the mean square error (MSE) of the sidelobes relative to the peak from a single point target was less than -70 dB. Changes in waveform duration and sampling rate had negligible effect on the error level. This error characteristic can be treated as a computational or self noise, added to the input thermal noise of the radar receiver. Quantization artifacts or noise peaks which occur at levels consistent with the mantissa quantization are below levels (-50 dB for 8 bits plus sign) which would normally cause difficulty in an operational system.