DocumentCode :
1086939
Title :
FCAT-II: A 50 ns/15 V alterable nonvolatile memory device—Part I: Experimental
Author :
Horiuchi, Masatada ; Katto, Hisao
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Volume :
30
Issue :
10
fYear :
1983
fDate :
10/1/1983 12:00:00 AM
Firstpage :
1369
Lastpage :
1375
Abstract :
A new structure for an n-channel Floating Si-gate Channel Corner Avalanche Transition nonvolatile memory device (FCAT-II) and its novel write-erase characteristics are described. The new structure is a modification of the previously reported FCAT (FCAT-I) memory device. The key improvement is better coupling between the floating gate and the control gate. This makes Fowler-Nordheim tunneling the major electron injection mechanism in the floating gate. The p+-p junctions placed outside the channel area are self-aligned with the floating gate and have an important role in crowding and raising the electron injection field. The device can operate in both write and erase modes at high-speed (≥ 50 ns) and low-voltage (≤15 V) conditions using only positive pulses. Another useful feature is the saturation of the high level threshold voltage independent of write pulse width greater than 50 ns. Reliability of this device is as good as that of FCAT-I.
Keywords :
Degradation; EPROM; Electrons; Nonvolatile memory; Random access memory; Read only memory; Read-write memory; Space vector pulse width modulation; Tiles; Tunneling;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1983.21301
Filename :
1483202
Link To Document :
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