Title :
A 470-MHz CMOS true single-phase clocked bit-serial arithmetic unit
Author :
Larsson-Edefors, Per
Author_Institution :
Dept. of Phys., Linkoping Univ., Sweden
fDate :
4/1/1994 12:00:00 AM
Abstract :
A two´s complement bit-serial arithmetic unit (AU) that operates at very high clock rates is presented in this paper. It is designed for a bit-serial SIMD data-path architecture and can perform several different arithmetic operations; for example sum-of-two-products. In order to attain a very high clock rate, the AU circuitry employs the true single-phase clocking (TSPC) technique, which encourages a high degree of pipelining. A 5-bit AU chip on an active area of 0.073 mm2 has been fabricated in a 1.0-μm standard CMOS process. Tests have verified correct chip operation up to a clock rate of 470 MHz at Vdd=5 V. At this frequency the AU power consumption is 11.5 mW
Keywords :
CMOS integrated circuits; digital arithmetic; integrated logic circuits; parallel processing; 1.0 micron; 11.5 mW; 470 MHz; 5 V; 5 bit; CMOS; SIMD data-path architecture; chip operation; clock rates; pipelining; sum-of-two-products; true single-phase clocked bit-serial arithmetic unit; two´s complement bit-serial arithmetic; Arithmetic; CMOS process; Circuits; Clocks; Distributed computing; Energy consumption; Gold; Hardware; High performance computing; Throughput;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
