DocumentCode :
1091836
Title :
A new vertical double diffused MOSFET—The self-aligned terraced-gate MOSFET
Author :
Ueda, Daisuke ; Takagi, Hiromitsu ; Kano, Gota
Author_Institution :
Matsushita Electronics Corporation, Osaka, Japan
Volume :
31
Issue :
4
fYear :
1984
fDate :
4/1/1984 12:00:00 AM
Firstpage :
416
Lastpage :
420
Abstract :
A new power MOSFET structure with a Self-aligned Terraced Gate (STGMOSFET) is demonstrated. The unique gate structure of the STGMOSFET reduces the parasitic gate capacitances, resulting in improved high-frequency performance. The STGMOSFET structure was used to design a 3.5 mm × 3.5 mm transistor. This chip had an on-resistance of 2.3 Ω and a 500-V source-drain breakdown voltage. It exhibited excellent high-frequency performance with a cut-off frequency of 100 MHz, and rise and fall times of 5 and 20 nS, respectively.
Keywords :
Cutoff frequency; Electrodes; Fabrication; Immune system; Impedance; Lapping; MOSFET circuits; Parasitic capacitance; Power MOSFET; Temperature;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/T-ED.1984.21543
Filename :
1483828
Link To Document :
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