DocumentCode :
1092061
Title :
Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism
Author :
Cheng, Chao ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN
Volume :
54
Issue :
2
fYear :
2007
Firstpage :
280
Lastpage :
290
Abstract :
Based on recently published low-complexity parallel finite-impulse response (FIR) filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subfilters in the previous parallel FIR structures are replaced by a second stage parallel FIR filter. The proposed 2-stage parallel FIR filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions
Keywords :
FIR filters; convolution; delay circuits; 2-stage parallel FIR filter structures; VLSI; fast convolution; finite-impulse response filter structures; iterated short convolution; Chaos; Clocks; Convolution; Costs; Data preprocessing; Delay; Finite impulse response filter; Hardware; Lead; Matrix decomposition; Fast convolution; VLSI; iterated short convolution (ISC); parallel finite-impulse response (FIR);
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2006.885976
Filename :
4089111
Link To Document :
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