DocumentCode :
1092091
Title :
Scaling law in ULSI contamination control
Author :
Hiraiwa, Atsushi ; Itoga, Toshihiko
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Volume :
7
Issue :
1
fYear :
1994
fDate :
2/1/1994 12:00:00 AM
Firstpage :
60
Lastpage :
67
Abstract :
The need for chemical contamination control for future LSI´s is investigated by considering device failure mechanisms. The allowable contamination density is calculated by deducing relationships between the contamination density and resultant defect density from experimental results. In the calculations LSI failures are classified into two groups according to the characteristics of failure-producing defects: macrotype and microtype. The former defects are macroscopic and fatal: a single defect causes a failure. A stricter contamination control is required for smaller devices similar to that predicted by conventional yield theory. This is due to increasing chip area. By contrast the latter defects are of atomic size, and a single defect is not fatal: devices fail when the defect density exceeds some threshold value. Transconductance degradation in MOS transistors due to interface traps and the resultant SRAM operation error is proposed as an example. The threshold defect (or contamination) density for the failure could be 1×1011 cm-2 in this model. The allowable contamination density abruptly decreases for a minimum pattern size smaller than 0.1 μm. This is due to increasing fluctuations of defect density in component devices. This failure might cause a bottleneck in developing gigabit memories
Keywords :
VLSI; circuit reliability; failure analysis; integrated circuit manufacture; LSI failures; MOS transistors; SRAM operation error; ULSI contamination control; chemical contamination; contamination density; defect density; device failure mechanisms; interface traps; model; scaling law; transconductance degradation; yield prediction; Chemicals; Contamination; Degradation; Failure analysis; Fluctuations; Large scale integration; MOSFETs; Random access memory; Transconductance; Ultra large scale integration;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/66.286832
Filename :
286832
Link To Document :
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